Integrated Circuit Memory Devices and Capacitors Having Carbon Nanotube Electrodes

ABSTRACT

An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conductive catalyst material. This catalyst material may be selected from the group consisting of iron, nickel and cobalt and alloys thereof.

REFERENCE TO PRIORITY APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/205,253, filed Aug. 16, 2005, which claims priority to Korean PatentApplication No. 2004-71892, filed Sep. 8, 2004, the disclosures of whichare hereby incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methodsof forming integrated circuit devices and, more particularly, tointegrated circuit devices having on-chip capacitors and methods offorming integrated circuit devices having on-chip capacitors.

BACKGROUND OF THE INVENTION

A carbon nanotube (CNT) has a tube structure in which carbon atoms arecombined with others in a form of a hexagonal lattice. The carbonnanotube may have a diameter of several nanometers. The carbon nanotubemay be known as a defect-free material having superior mechanicalstrength, high electrical selectivity, excellent field-emissionperformance, and efficient hydrogen storage capability. The carbonnanotube is usually manufactured by high synthesis technologies such asarc discharge, pyrolysis, laser deposition, plasma enhanced chemicalvapor deposition, thermal chemical vapor deposition, electrolysis, andflame synthesis.

Efforts to use the aforementioned properties of the carbon nanotube havebeen made in a variety of fields. For example, U.S. Patent PublicationNo. 2003/0100189 A1 discloses a method of forming a catalyst metal on asubstrate and growing a carbon nanotube thereon. At least one problemwith the method disclosed in this document is that it is difficult toobtain a carbon nanotube vertically oriented against the substrate.

SUMMARY OF THE INVENTION

Embodiments of the invention include a semiconductor memory devicehaving a cell transistor formed on a semiconductor substrate and havinga source region, a drain region, and a word line traversing an upperportion of a channel region provided between the source region and thedrain region. A bit line is electrically connected to the drain regionof the cell transistor via a bit line contact plug. A storage region iselectrically connected to the source region via a buried contact plug.The storage region includes a carbon nanotube.

Additional embodiments of the invention include methods of manufacturinga semiconductor memory device. These methods include forming a celltransistor on a semiconductor substrate. The cell transistor includes asource region, a drain region, and a word line traversing an upperportion of a channel region provided between the source region and thedrain region. An insulating layer is also formed on the substrate. Aburied contact plug is formed in the insulating layer. The buriedcontact plug is electrically connected to the drain region. A lowerelectrode having a carbon nanotube is formed on the buried contact plug.A step is then performed to form a storage dielectric layer on a surfaceof the lower electrode. An upper capacitor electrode is then formed onthe storage dielectric layer.

Still further embodiments of the invention include an integrated circuitdevice having an integrated circuit capacitor therein. This integratedcircuit capacitor includes first and second electrodes and at least onedielectric layer extending between the first and second electrodes. Thefirst electrode includes at least two carbon nanotubes and anelectrically conductive diffusion layer in gaps between the at least twocarbon nanotubes. The integrated circuit device further includes asemiconductor substrate and an electrically conductive plug. Thisconductive plug electrically connects the first electrode to thesemiconductor substrate. The capacitor further includes an electricallyconductive catalyst material. This electrically conductive catalystmaterial extends between the electrically conductive plug and the atleast two carbon nanotubes. This catalyst material may be selected fromthe group consisting of iron, nickel and cobalt and alloys thereof. Theconductive plug may also include a material selected from the groupconsisting of tungsten, titanium, tantalum and polysilicon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an integrated circuit memory deviceaccording to embodiments of the present invention.

FIGS. 2A-2G are cross-sectional views of intermediate structures thatillustrate methods of forming integrated circuit memory devices havingcarbon nanotube electrodes, according to embodiments of the presentinvention.

FIGS. 3A-3C are cross-sectional views of intermediate structures thatillustrate methods of forming integrated circuit memory devicesaccording to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present. Moreover, each embodimentdescribed and illustrated herein includes its complementary conductivitytype embodiment as well.

FIG. 1 is a cross-sectional view illustrating a semiconductor memorydevice according to a first embodiment of the present invention.Referring to FIG. 1, an active region is defined by trenches 101 a, 101b formed by shallow trench isolation. A gate is formed on the activeregion, and a source 103 and a drain 105 are formed in the activeregion. The source 103 and the drain 105 may be formed by a typical ionimplantation process using the gate as an implant. Also, the gateincludes a gate oxide film 107 and conduction material 109. Preferably,the gate oxide film 107 is made of SiO₂, and the conduction material 109is made of poly-silicon. The gate may be provided with a sidewall spacer111 and a hard mask layer 113, which protect the poly-silicon of thegate during subsequent etching processes and doping with a highconcentration of ions into the source and drain regions.

A transistor is defined by the source 103, the drain 105, and the gateprovided on the active region. Furthermore, a first interlayerinsulating layer 115 covering the transistor is formed thereon. Theupper surface of the first insulating interlayer 115 is provided with abit line 117, which is electrically connected to the drain 105 via a bitline contact plug 118. Preferably, the bit line 117 is provided with aconductor for electrical connection with the bit line contact plug 118and a bit line spacer for protecting the conductor.

On the upper surface of the bit line 117, a second interlayer insulatinglayer 119 is provided to fully cover the bit line 117. Subsequently, aburied contact plug 121 is provided by a self-aligned contact process.The self-aligned contact process is a technique that makes it possibleto form bit lines and word lines, and then form contact holes by usingthe bit lines and the word lines as an etching mask. In case the contactholes are filled with a conductive material, plugs are formed and theycan be electrically connected to the source or the drain of the activeregion located under the interlayer insulating layers.

On the buried contact plug 121 formed by the self-aligned contactprocess, a lower electrode 123 is formed. The lower electrode 123 has atleast one carbon nanotube therein. More specifically, the lowerelectrode 123 may be made of only one carbon nanotube or two or morecarbon nanotubes.

If the lower electrode 123 has two or more carbon nanotubes, a diffusionbarrier 125 may be formed to fill the gaps between the carbon nanotubes,and to prevent oxygen atoms contained in a dielectric material frombeing diffused into the lower electrode 123 and to facilitate a bondingbetween the lower electrode 123 and the dielectric film. The diffusionbarrier 125 may be made of a predetermined conductive material bychemical vapor deposition or atomic layer deposition. Specifically, onthe surface of the diffusion barrier 125, a dielectric film 127 isprovided. In addition, an upper electrode 129 is formed on the surfaceof the dielectric film 127. An etching protection layer 131 is alsoprovided under the upper electrode 129. The etching protection layer 131protects the second insulating interlayer 119 during an etching processfor forming the upper electrode 129. If the lower electrode 123 has onlyone carbon nanotube, a dielectric film may be provided on the surface ofthe carbon nanotube, and an upper electrode may be provided on thesurface of the dielectric film. Alternatively, the diffusion barrier isprovided on the surface of the carbon nanotube, and the upper electrodeis provided on the diffusion barrier.

FIGS. 2A through 2G are cross-sectional views illustrating a method ofmanufacturing a semiconductor memory device having a single carbonnanotube as a lower capacitor electrode, according to a secondembodiment of the present invention. Referring to FIG. 2A, a buriedcontact plug 203 is formed on a semiconductor substrate having a celltransistor, a first interlayer insulating layer (not shown) covering thecell transistor, a bit line (not shown) formed on the first interlayerinsulating layer, and a second interlayer insulating layer 201 coveringthe bit line.

A buried contact hole is formed in the second interlayer insulatinglayer 201. The buried contact hole may be formed by depositing aphotoresist layer (not shown) on the second interlayer insulating layer201 and then patterning the photoresist layer by a photolithographyprocess. By the patterning process, predetermined portions of the secondinterlayer insulating layer 201 are exposed. Then, anisotropic dryetching is applied to the exposed portions of the second interlayerinsulating layer 201 to define opening therein. Subsequently,anisotropic dry etching is applied to the first interlayer insulatinglayer disposed underneath the second insulating interlayer 201 tothereby expose a source region of a cell transistor. (See also FIG. 1,which shows a first interlayer insulating layer 115 and a secondinterlayer insulating layer 119 having a contact hole extendingtherethrough). Alternatively, a landing pad (not shown) made ofpoly-silicon may be provided on the source region of the celltransistor, and the aforementioned anisotropic dry etching may beapplied to expose the landing pad. As in the first embodiment, theburied contact hole may be formed by a self-aligned contact process.

The buried contact hole formed by the anisotropic dry etching is thenfilled with a conductive material, which is patterned to define a buriedcontact plug 203. The conductive material may be selected from a groupconsisting of W, Ti, Ta and poly-silicon. Preferably, the buried contactplug 203 is made of tungsten (W) due to its good step coverage. Also,the buried contact plug 203 may be formed by filling the buried contacthole and extending it to the upper surface of the second interlayerinsulating layer 201. If the buried contact plug 203 is made ofpoly-silicon, silicide (not shown) may be provided by depositing Ni orCo metal on the buried contact plug 203 and then performing heattreatment to convert the metal to a metal silicide.

Referring to FIG. 2B, an etching protection layer 205 is formed to fullycover the buried contact plug 203. Preferably, the etching protectionlayer 205 is made of SiN. The etching protection layer 205 may be formedto fully cover the buried contact plug 203 and the second interlayerinsulating layer 201. Referring to FIG. 2C, a third interlayerinsulating layer 207 is provided on the etching protection layer 205.The third interlayer insulating layer 207 is made of an insulationmaterial, and may be formed using a chemical vapor deposition (CVD)technique.

Referring to FIG. 2D, the third interlayer insulating layer 207 and theetching protection layer 205 are selectively etched in sequence toexpose the buried contact plugs 203. First, a photoresist layer (notshown) is deposited on the surface of the third interlayer insulatinglayer 207 and patterned by a typical photolithography process to definea photoresist pattern (not shown). This patterning allows predeterminedportions of the third interlayer insulating layer 207 to be exposed.Then, an anisotropic dry etching is applied to remove the exposedportions and expose the buried contact plug 203. The etched space isused as a guide pattern 209 for growing a carbon nanotube, as describedhereinbelow.

Referring to FIG. 2E, a catalyst metal particle 211 for growing a carbonnanotube is provided on each buried contact plug 203. The catalyst metalparticle 211 may be made of a material selected from a group consistingof Fe, Ni, Co and alloys thereof. The catalyst metal material is firstdeposited on the buried contact plug 203. In particular, the catalystmetal material is deposited on the buried contact plug 203, which is ata bottom surface of the guide pattern 209 for growing a carbon nanotube,sidewalls of the guide pattern 209, and on the photoresist pattern (notshown). Subsequently, the photoresist pattern and the catalyst metalmaterial deposited on the photoresist pattern are removed by chemicalmechanical polishing (CMP) to expose the third interlayer insulatinglayer 207. After CMP, the deposited catalyst metal material remains onlyin the guide pattern 209.

Then, an etching process is performed to provide a catalyst metalparticle 211 in each guide pattern 209. Preferably, the etching processmay be a wet etching process using an HF aqueous solution. Morespecifically, the substrate on which the catalyst metal material isdeposited can be dipped into the HF aqueous solution for several tens orhundreds seconds to perform a wet etching for the surface of thecatalyst metal material. The dipping time may be appropriatelycontrolled depending on the number and the sizes of the catalyst metalparticles that will be formed. The dipping time necessary to form onecatalyst metal particle 211 in the guide pattern 209 may be 10 through200 seconds.

After the wet etching using the HF aqueous solution, dry etching usingan NH3 gas may be performed for the directional growth of the carbonnanotube. The wet etching using the HF aqueous solution can provide thecatalyst metal particle 211. However, its surface may be rough.Therefore, an NH3 gas is supplied to the substrate and guide patterns209 with a predetermined flux for several tens of minutes to obtain thecatalyst metal particle 211 having a smooth hemispherical shape. Byperforming wet etching using the HF aqueous solution and/or the dryetching using an NH3 gas, it is possible to remove the catalyst metalmaterials formed on the side-walls of the guide patterns 209.

Referring to FIG. 2F, the catalyst metal particle 211 in each guidepattern 209 is used to grow a carbon nanotube 213, which will be usedfor a lower capacitor electrode of a storage capacitor. While the carbonnanotube 213 grows, the guide pattern 209 allows the carbon nanotube togrow in a vertical direction. The growth of the carbon nanotube 213 maybe performed by plasma enhanced chemical vapor deposition (PECVD) orthermal chemical vapor deposition. PECVD is a method of performing glowdischarge of reactive gases by using direct currents or high frequencyelectric fields applied between two electrodes. The semiconductorsubstrate for synthesizing each carbon nanotube 213 may be positioned onthe lower electrode that is grounded, and the reactive gases aresupplied to the upper electrode. The reactive gas may include CH₄, C₂H₂,or C₂H₄. Preferably, the temperature for synthesizing the carbonnanotube 213 is within a range of 700° C. through 950° C. In contrast,thermal chemical vapor deposition is a method of growing the carbonnanotube 213 by locating the semiconductor substrate in a reactorchamber and supplying the reactive gases within a predeterminedtemperature range into the inside of the reactor chamber. Preferably,the reaction temperature may be within a range of 500° C. through 950°C., and the reactive gas may include a carbonized gas such as C₂H₂, CH₄,C₂H₄, or CO.

Referring to FIG. 2G, the third interlayer insulating layer 207 isremoved after the carbon nanotube 213 forming the storage lowerelectrode is synthesized. Preferably, the third interlayer insulatinglayer 207 may be removed by a wet etching process in which the etchingprotection layer 205 is used as an etching mask. After removal of thethird interlayer insulating layer 207, the carbon nanotube 213 formed onthe buried contact plug 203 and the etching protection layer 205 formedbetween the buried contact plugs are exposed. Subsequently, a dielectricfilm 215 is provided on the surface of the carbon nanotube 213.Alternatively, a diffusion barrier (not shown) may be formed on thesurface of the carbon nanotube 213 before the dielectric film 215 isformed. The diffusion barrier prevents oxygen contained in thedielectric material from being diffused into the carbon nanotube 213,and facilitates a bonding between the dielectric film 215 and the carbonnanotube 213, which acts as a lower capacitor electrode. The diffusionbarrier may be made of TiN.

The entire surface of the etching protection layer 205 and thedielectric film 215 are covered with a conducting material to form anupper capacitor electrode 217. As a result, it is possible to provide asemiconductor memory device having a carbon nanotube 213 that operatesas a capacitor electrode with a memory cell. Alternatively, the methodof growing the carbon nanotube 213 using the guide pattern 209 may bemodified. More specifically, a process of removing a portion of thecarbon nanotube protruding from the third interlayer insulating layer207 (see FIG. 2F), may be added after the carbon nanotube 213 having apredetermined length is synthesized. The length of the carbon nanotube217 can be controlled by chemical mechanical polishing. Processes ofdepositing the dielectric film 213 and forming the upper electrode 207after controlling the length of the carbon nanotube 213 are thenperformed as described herein above.

FIGS. 3A through 3C are cross-sectional views for describing a method ofmanufacturing a semiconductor memory device shown in FIG. 1 according toanother embodiment of the present invention. Referring to FIG. 3A, twoor more catalyst metal particles 311 are provided within each guidepattern 309 that is formed on a semiconductor substrate. Since processesof forming the guide pattern 309 for growing a carbon nanotube aresimilar to those shown in FIGS. 2A through 2D, their detaileddescription will not be provided again. First, a catalyst metal materialis deposited on the buried contact plug 303 formed in the guide pattern309. The catalyst metal material may be selected from a group consistingof Fe, Ni, Co and alloys thereof. Then, an etching process for formingcatalyst metal particles 311 is performed. Preferably, the etchingprocess may be a wet etching process using an HF aqueous solution. Morespecifically, a semiconductor substrate on which the catalyst metalmaterial is deposited is dipped into the HF aqueous solution for severaltens or hundreds seconds to perform a wet etching of the surface of thecatalyst metal material. The dipping time may be appropriatelycontrolled according to the number and the sizes of the catalyst metalparticles that will be formed. As shown in FIG. 3A, the dipping timenecessary to form two or more catalyst metal particles 311 in the guidepattern 309 may be 10 through 200 seconds.

After the wet etching using the HF aqueous solution, a dry etching usingan NH3 gas may be performed for the directional growth of the carbonnanotubes. The wet etching using the HF aqueous solution can providecatalyst metal particles 311. However, their surfaces may be rough. Toremedy this roughness, an NH3 gas is supplied to the semiconductorsubstrate with a predetermined flux for at least several minutes toobtain a plurality of catalyst metal particles 311 having smoothhemispherical shapes.

Referring to FIG. 3B, the catalyst metal particles in the guide pattern309 are used to grow carbon nanotubes 313 for a lower capacitorelectrode. While the carbon nanotubes 313 grow, the guide pattern 309 isused to allow the carbon nanotubes 313 to grow in a vertical direction.The growth of the carbon nanotubes 313 is performed by plasma enhancedchemical vapor deposition (PECVD) or thermal chemical vapor deposition.Among a plurality of carbon nanotubes 313, van der waal's forces andsteric hindrance are present. For this reason, the vertically orientedcarbon nanotubes 313 are separated from each other. The minimum intervalbetween the separated carbon nanotubes 313 is about 0.34 nm.Subsequently, the space between the separated carbon nanotubes 313 andthe space between sidewalls of the guide pattern 309 are filled with aconductive material. The conductive material may function as a diffusionbarrier 315. The diffusion barrier 315 prevents oxygen contained in adielectric film from being diffused into the carbon nanotubes 313, andfacilitates a bonding between the dielectric film and the carbonnanotubes 313 corresponding to the lower electrode. The diffusionbarrier 315 may be made of TiN.

Referring to FIG. 3C, the surface of the diffusion barrier 315 iscovered with a dielectric film 317, and the upper electrode 319 isprovided on the dielectric film 317. More specifically, the thirdinterlayer insulating layer 307 can be removed by wet etching. As aresult, the diffusion barrier 315, the etching protection layer 305, andthe lower electrode having the carbon nanotubes 313 are exposed. Then,the dielectric film 317 is deposited on the exposed diffusion barrier315. Subsequently, the upper capacitor electrode 319 is provided tofully cover the surfaces of the deposited dielectric film 317 and theetching protection layer 305. As a result, it is possible to provide asemiconductor memory device having carbon nanotubes 313 that formcapacitor electrodes.

Alternatively, the method of growing the carbon nanotubes 313 using theguide pattern 309 may be differently embodied. More specifically, aprocess of removing portions of the carbon nanotubes 313 protruding fromthe third interlayer insulating layer may be added after the carbonnanotubes of a predetermined length are synthesized. The length of thecarbon nanotubes 313 can be controlled by chemical mechanical polishing.Processes for depositing the dielectric film 315 and forming the uppercapacitor electrode after controlling the length of the carbon nanotubes313 are similar to those of the aforementioned embodiment.

Thus, as described herein, guide patterns are used to induce thedirectional growth of carbon nanotubes, and catalyst metal particles areused to support formation of a lower capacitor electrode of asemiconductor memory device. As a result, it is possible to obtain asemiconductor memory device having a carbon nanotube used as a lowercapacitor electrode. The carbon nanotube has a cylindrical shape with ahigh aspect ratio. Therefore, it is possible to obtain a storagecapacitor having high capacitance. Since a work function of the carbonnanotube is typically 4.7 through 5.0 eV, it is possible to reduceleakage currents that can occur between the lower capacitor electrodeand the dielectric film. Furthermore, since the carbon nanotube has a πbonding structure which is chemically stable, it provides tolerance ofchemical influences in subsequent fabrication processes and excellentstability for heat flux.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims. The exemplary embodimentsshould be considered in descriptive sense only and not for purposes oflimitation. Therefore, the scope of the invention is defined not by thedetailed description of the invention but by the appended claims, andall differences within the scope will be construed as being included inthe present invention.

1. An integrated circuit device, comprising: an integrated circuitcapacitor having first and second electrodes and at least one dielectriclayer extending between the first and second electrodes, said firstelectrode comprising at least two carbon nanotubes and an electricallyconductive diffusion barrier layer interposed between the carbonnanotube and the dielectric layer.
 2. The device of claim 1, furthercomprising: a semiconductor substrate; and an electrically conductiveplug electrically connecting said first electrode to said semiconductorsubstrate.
 3. The device of claim 2, further comprising an electricallyconductive catalyst material extending between said electricallyconductive plug and the at least two carbon nanotubes.
 4. The device ofclaim 3, wherein the catalyst material is selected from the groupconsisting of iron, nickel and cobalt and alloys thereof.
 5. The deviceof claim 4, wherein said electrically conductive plug comprises amaterial selected from the group consisting of tungsten, titanium,tantalum and polysilicon.
 6. The device of claim 2, wherein saidelectrically conductive plug comprises a material selected from thegroup consisting of tungsten, titanium, tantalum and polysilicon.
 7. Anintegrated circuit device, comprising: a semiconductor substrate havinga field effect transistor adjacent a surface thereof, said field effecttransistor comprising source and drain regions in said semiconductorsubstrate and an insulated gate electrode on the surface, between thesource and drain regions; a first interlayer insulating layer on saidsemiconductor substrate; a bit line on said first interlayer insulatinglayer; a bit line contact plug that extends through said firstinterlayer insulating layer and electrically connects said bit line tothe drain region; a second interlayer insulating layer on said firstinterlayer insulating layer and said bit line; a buried contact plugthat extends through said first and second interlayer insulating layersand contacts the source region; and a storage capacitor on said buriedcontact plug, said storage capacitor comprising a lower carbon nanotubeelectrode electrically connected to said buried contact plug, adielectric layer on the lower carbon nanotube electrode and an upperelectrode on the dielectric layer.
 8. The device of claim 7, furthercomprising an electrically conductive catalyst material extendingbetween said buried contact plug and the lower carbon nanotubeelectrode.
 9. The device of claim 8, wherein the catalyst material isselected from the group consisting of iron, nickel and cobalt and alloysthereof.
 10. The device of claim 9, wherein said buried contact plugcomprises a material selected from the group consisting of tungsten,titanium, tantalum and polysilicon.